1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the techniques for reducing chip-package interactions caused by thermal mismatch between the chip and the package.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable base materials for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like. The individual integrated circuits are arranged in an array on the wafer, wherein most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In the attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with a low-k dielectric material, has become a frequently used alternative in the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to implement the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to a reduced cross-sectional area. For this reason, traditional dielectrics, such as silicon dioxide (k>4) and silicon nitride (k>7), are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of these sensitive dielectric materials and their adhesion to other materials.
In addition to the problems of reduced mechanical stabilities of advanced dielectric materials having a dielectric constant of 3.0 and significantly less, device reliability may be affected by these materials during operation of sophisticated semiconductor devices due to an interaction between the chip and the package caused by a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly, a contact technology may be used in connecting the package carrier to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a wire, in the flip chip technology, a respective bump structure may be formed on the last metallization layer, for instance, using aluminum as a terminal metal in combination with a solder material which may be brought into contact with respective contact pads of the package. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the terminal metal formed on the last metallization layer and the contact pads of the package carrier. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the IO (input/output) capabilities, which may be required for complex integrated circuits, such as CPUs, storage memories and the like. During the corresponding process sequence for connecting the bump structure with a package carrier, a certain degree of pressure and/or heat may be applied to the composite device so as to establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower lying metallization layers, which may typically include low-k dielectrics or even ultra low-k (ULK) dielectric materials, thereby significantly increasing the probability of creating defects in the form of cracks, delamination and the like, due to reduced mechanical stability and adhesion to other materials.
Moreover, during operation of the finished semiconductor device attached to a corresponding package substrate, significant mechanical stress may occur due to a significant mismatch in the thermal expansion behavior of the silicon-based semiconductor chip and the package substrate, since, in volume production of sophisticated integrated circuits, economic constraints typically require the usage of specified substrate materials for the package, such as organic materials, which typically may exhibit a different thermal conductivity and a coefficient of thermal expansion compared to the silicon chip.
With reference to FIGS. 1a-1b, a typical conventional configuration of a semiconductor device including a solder bump structure will now be described in more detail.
FIG. 1a schematically illustrates a top view of the configuration or layout of a semiconductor device 100 in which the mechanical and electrical connection between a package and the device 100, i.e., a specific chip or die 101, is to be established on the basis of a solder bump structure. For this purpose, an appropriate distribution of contact elements 110 across the entire area of the die 101 may be provided, wherein, as previously discussed, nearly the entire area of the die 101 is available for appropriately positioning the contact elements 110. In this manner, a very complex contact structure may be accomplished, wherein each of the contact elements 110 may be connected to a counterpart contact pad or bump of a corresponding package substrate during a single manufacturing process, contrary to corresponding wire bond techniques in which a bond wire may have to be connected to bond pads of the chip and the package in a substantially sequential manner.
FIG. 1b schematically illustrates a cross-sectional view of the device 100 according to the line Ib in FIG. 1a. As illustrated, the device 100 comprises the die or chip 101, which may be understood as the basic substrate for forming thereabove circuit elements and the like. The substrate 101 is typically provided in the form of an insulating substrate, a semiconductor material and the like. It should be appreciated that, in and above the substrate 101, typically, a plurality of circuit elements, such as transistors, capacitors, resistors and the like, are provided in accordance with the circuit function to be implemented in the device 100. For convenience, any such circuit elements, which may include elements with critical dimensions of 50 nm and less in sophisticated devices, are not shown in FIG. 1b. As discussed above, due to the complex layout of electronic circuits implemented in the semiconductor device 100, a complex metallization system 120 is typically required, which may comprise a plurality of metallization layers stacked on top of each other, wherein, for convenience, a metallization layer 130 and a metallization layer 140 are depicted. For instance, the metallization layer 130 may be comprised of a dielectric material 131, such as a low-k dielectric material, a ULK material and the like, in which metal lines and vias 132 are embedded that are typically comprised of copper, in combination with appropriate conductive barrier materials, to provide reliable copper confinement. It should be appreciated that each metallization layer of the system 120 may not necessarily comprise a sensitive low-k dielectric material since different metallization levels may require different performance characteristics, for instance with respect to drive current capability and signal propagation delay. However, at any rate, typically, a plurality of metallization layers may comprise a sensitive low-k dielectric material, thereby reducing the overall mechanical stability, as discussed above. Furthermore, the metallization layer 140 represents the “last” metallization layer and comprises any appropriate dielectric material 141 including metal regions 142, which may represent contact pads for connecting to a contact structure or bump structure 150, which may actually represent the interface for connecting the device 100 with a package substrate (not shown). The contact or bump structure 150 typically comprises a passivation layer 151, which may thus “passivate” the metallization system 120, wherein, typically, a plurality of dielectric materials, such as silicon dioxide, silicon oxynitride, silicon nitride, are used to provide the desired characteristics in view of chemical and mechanical stability. Moreover, a further dielectric material, such as a polyimide 152, is formed on the passivation material 151. The materials 151 and 152 are patterned in such as way that an opening 150A is aligned to at least a portion of the contact pad 142 of the last metallization layer 140. As explained before, in sophisticated metallization systems, such as the system 120, copper is preferably used, which, however, may not be compatible with well-established process techniques and materials as have been used in complex metallization systems formed on the basis of aluminum. For this reason, frequently, a further metal material 153, which is also referred to as a terminal metal, in the form of aluminum, is provided to act as an interface between the sensitive copper material of the pad 142 and the contact element 110. In this manner, well-established materials and techniques may be applied for forming the contact element 110, for instance by providing efficient underbump metallization systems 154, for instance based on chromium, copper, tungsten and the like.
On the other hand, providing aluminum as the terminal metal 153 may require additional resources for depositing, patterning and cleaning the device 100 prior to actually forming the contact element 110. That is, after forming the metallization system 120 on the basis of well-established process techniques, the passivation material 151 is deposited and patterned, followed by the deposition of the aluminum material, which may be associated by the deposition of an appropriate barrier material, such as titanium, titanium nitride and the like. Thereafter, a complex patterning process is to be applied, for instance, by applying an etch chemistry on the basis of bromine and the like. Consequently, corresponding precursor materials and deposition and etch tools are required for providing the terminal metal 153. Thereafter, a well-established process sequence is applied for depositing the polyimide material 152 and patterning the same, followed by the deposition of the underbump materials 154. Thereafter, a deposition mask is typically applied and a solder bump material in the form of a lead-containing material is deposited on the basis of electroplating techniques, followed by the removal of the deposition mask and the patterning of the underbump material 154. After separating the semiconductor device 100 into individual chips 101, a connection to an appropriate package substrate may be accomplished by mechanically coupling the device 100 and the package substrate and reflowing the contact element 110, thereby obtaining the desired intermetallic connection between the element 110 and the corresponding contact pad of the package substrate, which may also comprise a solder bump, depending on the overall process strategy. Finally, any appropriate fill material may be provided between the chip 101, i.e., the contact structure 150 and the package substrate, so as to enhance mechanical, chemical and thermal stability of the composite device.
As discussed above, during the formation of the device 100, during the process of connecting the device 100 with a package substrate, and finally during operation of the composite semiconductor device, significant mechanical stress may be applied to the metallization system 120 via the contact structure 150, i.e., via the contact elements 110, wherein a certain degree of resilience of the contact elements 110, i.e., the lead-containing solder material, may result in a certain degree of “buffer effect.”
However, upon introducing so-called lead-free solder materials, for instance in view of environmental regulations and the like, and also in an attempt to further improve the thermal and electrical performance of the contact structure 150, for instance by providing copper pillars instead of the contact elements 110, the mechanical stress in the metallization system 120 may be even further enhanced since, typically, these materials may exhibit a lesser degree of resilience, thereby transferring significantly increased shear forces into the last metallization layer 140.
Consequently, in many conventional approaches, the increase of the mechanical stress in the metallization system 120 may require the usage of dielectric materials of superior mechanical stability, thereby, however, typically increasing the dielectric constant and thus reducing the overall electrical performance of the metallization system 120.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.